Feero and P. Yin, T. Xu, P.
Liljeberg, and H. Jiang, M. Marek-sadowska, and S. Nassif , Benefits and costs of power-gating technique , International Conference on Computer Design , pp. Farrokhbakht, M. Taram, B. Khaleghi, and S. Das, S. Narayanasamy, S. Satpathy, and R. Dreslinski , Catnap: energy proportional multiple network-on-chip , Proceedings of the 40th annual international symposium on Computer architecture , pp.
Muhammad, M. El-moursy, A. El-moursy, and A. Refaat , Optimization for traffic-based virtual channel activation low-power noc , 5th International Conference on Energy Aware Computing Systems Applications , pp. Parikh, R.
Das, and V. Zhan, J. Ouyang, F. Ge, J. Zhao, and Y. Chen, E. Chang, H.
Hsin, K. Chen, and A. Palesi, G. Longo, S. Signorino, R. Holsmark, S. Kumar et al. Samman, T.
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Hollstein, and M. Glesner , Runtime contention and bandwidth-aware adaptive routing selection strategies for networks-onchip , IEEE Transactions on Parallel and Distributed Systems , vol. Charif, N. Zergainoh, and M. Hu and R. Taassori and S. Hessabi , Low power encoding in nocs based on coupling transition avoidance , Digital System Design, Architectures, Methods and Tools, DSD ' Stan and W. Shin, S. Chae, and K.
System on a chip
Choi , Partial bus-invert coding for power optimization of system level bus , Proceedings. Taassori, M.
Taassori, and S. Uysal , Mflp: a low power encoding for on chip networks , Design Automation for Embedded Systems , vol. Ascia, F. Fazzino, and V. Jafarzadeh, M. The key advantages of QuT network are simplicity and lower power consumption. QuT demonstrates good scalability with significantly lower power and competitive latency. Article :.
DOI: Need Help? Jose and Priyadarsan Patra J. Nandy J. Dueck, and Alexandre C. Hasan J. Sree Ranjani and M. Nirmala Devi J.
Journal of Low Power Electronics
Jose, and Priyadarsan Patra J. Indira and M. Kamaraju J. Galapon, Mark Allen D.